Simulation of RRAM memory circuits, a Verilog-A compact modeling approach

Gerardo Gonzalez

G. González-Cordero, J. B. Roldán, and F. Jimenez-Molinos, “Simulation of RRAM memory circuits, a Verilog-A compact modeling approach,” in XXXI edition of the Design of Circuits and Integrated Systems Conference (DCIS), 2016 in Granada, Spain. DOI: 10.1109/DCIS.2016.7845386

Abstract
Three different compact models for resistive RAM are introduced in this work. The role of the conductive filaments ohmic resistance is introduced for different filament shapes, affecting the voltage at the gap between the filament tip and the electrode, and therefore the device hopping current. The temperature behavior of the devices under study is also described with a different degree of accuracy. These models have been implemented in Verilog-A in the ADS circuit simulator (Keysight Technologies) to analyze several non-volatile memory circuits. First, a single memory cell, making use of a NMOS transistor is studied accounting for the differences of the three RRAM models, and later on a 3×3 memory matrix is analyzed.
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